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INTEGRATED CIRCUITS
DATA SHEET
PCA3354C; PCD3354A 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
Product specification Supersedes data of 1996 May 09 File under Integrated Circuits, IC03 1996 Dec 18
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2 7.3 7.4 7.5 7.6 8 9 10 11 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FREQUENCY GENERATOR Frequency generator derivative registers Melody output (P1.7/MDY) DTMF clock divider and output (DP1.7/DCO) Frequency registers DTMF frequencies Modem frequencies Musical scale frequencies EEPROM AND TIMER 2 ORGANIZATION EEPROM registers EEPROM latches EEPROM flags EEPROM macros EEPROM access Timer 2 DERIVATIVE INTERRUPTS TIMING RESET IDLE MODE STOP MODE SUMMARY OF I/O PORTS AND MASK OPTIONS SUMMARY OF DERIVATIVE REGISTERS HANDLING LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
PCA3354C; PCD3354A
1996 Dec 18
2
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
1 FEATURES 2
PCA3354C; PCD3354A
GENERAL DESCRIPTION
* 8-bit CPU, ROM, RAM, EEPROM and I/O; all in a 44-lead quad flat package * 8 kbytes ROM; 256 bytes RAM * 256 bytes Electrically Erasable Programmable Read Only Memory (EEPROM) * Over 100 instructions (based on MAB8048) all of 1 or 2 cycles * 36 quasi-bidirectional I/O port lines * 8-bit programmable Timer/event counter 1 * 8-bit reloadable Timer 2 * Three single-level vectored interrupts: - external - 8-bit programmable Timer/event counter 1 - derivative; triggered by reloadable Timer 2 * Two test inputs, one of which also serves as the external interrupt input * DTMF, modem, musical tone generator * Reference for supply and temperature-independent tone output * Filtering for low output distortion (CEPT compatible) * Melody output for ringer application * Programmable DTMF clock divider * Power-on-reset * Stop and Idle modes * Supply voltage: 1.8 to 6 V (DTMF tone output and EEPROM erase/write from 2.5 V) * CPU clock frequency: 1 to 16 MHz (3.58 MHz or 10.74 MHz for DTMF) * Operating ambient temperature: - -25 to +70 C (PCD3354A) - 0 to 50 C (PCA3354C) * Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION (see note 1)
This data sheet details the specific properties of the PCA3354C and PCD3354A. The shared properties of the PCD33xxA family of microcontrollers are described in the "PCD33xxA family" data sheet, which should be read in conjunction with this publication. The PCA3354C and PCD3354A are microcontrollers oriented towards telephony applications. They include 8 kbytes ROM, 256 bytes RAM, 36 I/O lines, and an on-chip generator for dual tone multifrequency (DTMF), modem and musical tones. In addition to dialling, the generated frequencies can be made available as square waves for melody generation, providing ringer operation. The PCA3354C and PCD3354A also incorporate 256 bytes of EEPROM, permitting data storage without battery backup. The EEPROM can be used for storing telephone numbers, particularly for implementing redial functions. The differences between PCA3354C and PCD3354A are shown in Table 1. The instruction set is similar to the MAB8048 and is a sub-set of that listed in the "PCD33xxA family" data sheet. Table 1 Differences: PCA3354C and PCD3354A VPOR fixed at 2.0 V 0.3 V (1.2 to 3.6 V) 0.5 V(1) AMBIENT TEMP. RANGE 0 to 50 C -25 to +70 C
TYPE PCA3354C PCD3354A Note
1. See Chapter 13, Table 24.
PACKAGE TYPE NUMBER NAME PCA3354CH PCD3354AH Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and the ROM mask options. 1996 Dec 18 3 QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm VERSION SOT205-1
4
PCA3354C; PCD3354A
Product specification
Fig.1 Block diagram.
handbook, full pagewidth
1996 Dec 18
DP1.0 to DP1.7/DCO P0.0 to P0.7 8 PORT 0 BUFFER PORT 0 FLIP-FLOP DER. PORT 0 FLIP-FLOP DECODE DER. PORT 0 BUFFER 8 DP0.0 to DP0.7 8 fDTMF DER. PORT 1 BUFFER PORT 1 FLIP-FLOP PORT 1 BUFFER DER. PORT 1 FLIP-FLOP 8 P1.0 to P1.7/MDY
P2.0 to P2.3
TONE
Philips Semiconductors
BLOCK DIAGRAM
4
PORT 2 BUFFER
FILTER
PORT 2 FLIP-FLOP
PCA3354C PCD3354A
RESIDENT ROM 8 kbytes
SINE WAVE GENERATOR
INTERNAL CLOCK FREQ. 30 MEMORY BANK FLIP-FLOPS 32 T1 8 8 5 8 8 8 8 8 TIMER/ EVENT COUNTER PROGRAM STATUS WORD 8 HIGHER PROGRAM COUNTER LOWER PROGRAM COUNTER
HGF REGISTER
LGF REGISTER
DTMF-CLOCK & MELODY CONTROL REGISTER 8
4
8
8
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
8 8 8 8
8
8
8
8
8
8
8
8
8 MULTIPLEXER
TIMER 2 RELOAD REGISTER INTERRUPT LOGIC ACCUMULATOR timer interrupt derivative interrupt ARITHMETIC TEMPORARY REGISTER 2 INSTRUCTION REGISTER AND DECODER TEMPORARY REGISTER 1 RAM ADDRESS REGISTER
TIMER 2 REGISTER
EEPROM CONTROL REGISTER EEPROM DATA TRANSFER
4
LOGIC UNIT T1 CE/T0 CONDITIONAL BRANCH STOP CONTROL AND TIMING CE/T0 RESET INITIALIZE INTERRUPT XTAL1 XTAL2 IDLE LOGIC ACC TIMER FLAG CARRY external interrupt DECIMAL ADJUST OSCILLATOR
EEPROM ADDRESS REGISTER
REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 D E C O D E 8 LEVEL STACK (VARIABLE LENGTH) OPTIONAL SECOND REGISTER BANK
EEPROM 256 bytes
POWER-ON-RESET
VPOR
DATA STORE
RESET
ACC BIT TEST
RESIDENT RAM ARRAY 256 bytes
MED265
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
5 5.1 PINNING INFORMATION Pinning
PCA3354C; PCD3354A
handbook, full pagewidth
43 P1.7/MDY
37 TONE
38 VDD
42 P1.6
34 P1.1
41 P1.5
35 P1.2
44 P2.0
40 P1.4
36 VSS
39 P1.3
P2.1 P2.2 P2.3 DP0.0 DP0.1 DP0.2 DP0.3 DP0.4 DP0.5
1 2 3 4 5 6 7 8 9
33 P1.0 32 P0.7 31 P0.6 30 P0.5 29 P0.4
PCA3354CH PCD3354AH
28 XTAL2 27 XTAL1 26 P0.3 25 P0.2 24 P0.1 23 P0.0
DP0.6 10 DP0.7 11
DP1.6 21
DP1.7/DCO 22
CE/T0 12
T1 13
RESET 14
DP1.0 15
DP1.1 16
DP1.2 17
DP1.3 18
DP1.4 19
DP1.5 20
MED266
Fig.2 Pin configuration.
1996 Dec 18
5
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
5.2 Pin description
PCA3354C; PCD3354A
Table 2
SOT205-1 package (for information on parallel I/O ports, see Chapter 13) PIN 1 to 3 4 to 11 12 13 14 22 23 to 26 27 28 29 to 32 33 to 35 36 37 38 39 to 42 43 44 TYPE I/O I/O I I I I/O I/O I/O I O I/O I/O P O P I/O I/O I/O DESCRIPTION 3 bits of Port 2: 4-bit quasi-bidirectional I/O port Derivative Port 0: 8-bit quasi-bidirectional I/O port Chip Enable or Test 0 input Test 1/count input of 8-bit Timer/event counter 1 reset input 7 bits of Derivative Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Derivative Port 1: 8-bit quasi-bidirectional I/O port; or DTMF clock output 4 bits of Port 0: 8-bit quasi-bidirectional I/O port crystal oscillator/external clock input crystal oscillator output 4 bits of Port 0: 8-bit quasi-bidirectional I/O port 3 bits of Port 1: 8-bit quasi-bidirectional I/O port ground DTMF output positive supply voltage 4 bits of Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output 1 bit of Port 2: 4-bit quasi-bidirectional I/O port
SYMBOL P2.1 to P2.3 DP0.0 to DP0.7 CE/T0 T1 RESET DP1.7/DCO P0.0 to P0.3 XTAL1 XTAL2 P0.4 to P0.7 P1.0 to P1.2 VSS TONE VDD P1.3 to P1.6 P1.7/MDY P2.0
DP1.0 to DP1.6 15 to 21
1996 Dec 18
6
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
6 FREQUENCY GENERATOR
PCA3354C; PCD3354A
The TONE output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. In addition to DTMF and modem frequencies, two octaves of musical scale in steps of semitones are available. Their frequencies are provided either in purely sinusoidal form on the TONE output or as a square wave on the port line P1.7/MDY. The latter is typically for ringer applications in telephone sets. If no frequency output is selected the TONE output is in 3-state mode.
A versatile frequency generator section with built-in programmable clock divider is provided (see Fig.3). The clock divider allows the DTMF section to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 13 x fxtal) depending on the state of the divider control bit DIV3 (see Table 5). The frequency generator includes precision circuitry for dual tone multifrequency (DTMF) signals, which is typically used for tone dialling telephone sets. 6.1 6.1.1 Frequency generator derivative registers HIGH AND LOW GROUP FREQUENCY REGISTERS
Table 3 gives the addresses, symbols and access types of the High Group Frequency (HGF) and Low Group Frequency (LGF) registers, used to set the frequency output. Table 3 Hexadecimal addresses, symbols, access types and bit symbols of the frequency registers REGISTER SYMBOL HGF LGF ACCESS TYPE W W BIT SYMBOLS 7 H7 L7 6 H6 L6 5 H5 L5 4 H4 L4 3 H3 L3 2 H2 L2 1 H1 L1 0 H0 L0
REGISTER ADDRESS 11H 12H 6.1.2 Table 4 7 0 Table 5 BIT 7 to 3 2
CLOCK AND MELODY CONTROL REGISTER (MDYCON) Clock and Melody Control Register, MDYCON (address 13H; access type R/W) 6 0 5 0 4 0 3 0 2 EDCO 1 DIV3 0 EMO
Description of MDYCON bits SYMBOL - EDCO These bits are set to a logic 0. Enable DTMF clock output. If bit EDCO = 0, then DP1.7/DCO is a general purpose derivative port line. If bit EDCO = 1, then DP1.7/DCO is the DTMF clock output. EDCO = 1 does not inhibit the port instructions for DP1.7/DCO. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of DP1.7/DCO must remain set to avoid conflicts between DTMF clock and port outputs. Enable DTMF clock divider. If bit DIV3 = 0, then the DTMF clock fDTMF = fxtal. If bit DIV3 = 1, then fDTMF = 13 x fxtal. Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line. If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY must remain set to avoid conflicts between melody and port outputs. When the HGF contents are zero while EMO = 1, P1.7/MDY is in the HIGH state. DESCRIPTION
1 0
DIV3 EMO
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
handbook, full pagewidth
fxtal
CLOCK DIVIDER
fDTMF
PORT/CLOCK OUTPUT LOGIC
DP1.7/ DCO
8
CLOCK AND MELODY CONTROL REGISTER square wave
PORT/MELODY OUTPUT LOGIC
P1.7/ MDY
8 HGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER DAC SWITCHED CAPACITOR BANDGAP VOLTAGE REFERENCE DAC SWITCHED CAPACITOR LOW-PASS FILTER
8 INTERNAL BUS
RC LOW-PASS FILTER
MGB782
TONE
8 LGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER
Fig.3 Block diagram of the frequency generator, melody output (P1.7/MDY) and DTMF clock output (DP1.7/DCO).
6.2
Melody output (P1.7/MDY)
6.3
DTMF clock divider and output (DP1.7/DCO)
The melody output (P1.7/MDY) is very useful for generating musical notes when a purely sinusoidal signal is not required, such as for ringer applications. The square wave (duty cycle = 1223 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the HGF register (Table 3). However, even higher frequency notes may be produced since the low-pass filtering on the TONE output is not applied to the P1.7/MDY output. This results in the minimum decimal value x in the HGF register (see equation in Section 6.4) being 2 for the P1.7/MDY output, rather than 60 for the TONE output. A sinusoidal TONE output is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves with x < 60 will not appear at the TONE output. Since the melody output is shared with P1.7, the port flip-flop of P1.7 has to be set HIGH before using the melody output. This is to avoid conflicts between melody and port outputs. The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 13, Table 24.
The DTMF clock divider allows the DTMF part to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 13 x fxtal) depending on the state of the divider control bit DIV3 in register MDYCON. For low power applications, a 3.58 MHz quartz crystal or PXE resonator can be chosen together with the divide-by-one function of the clock divider. For other applications a 10.74 MHz quartz crystal or PXE resonator may be chosen together with the divide-by-three function of the clock divider. This triples the program speed of the microcontroller, thereby keeping the assumed DTMF frequency of 3.58 MHz. Since a 3.58 MHz clock is needed for peripheral telephony circuits such as the analog voice scrambler/descrambler PCD4440T, a switchable DTMF clock output is provided depending on the state of the enable clock output bit EDCO in register MDYCON.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
If EDCO = 1 and DIV3 = 1 in the MDYCON register: a square wave with the frequency fDTMF = 13 x fxtal is output on the derivative port line DP1.7/DCO. If EDCO = 1 and DIV3 = 0: a square wave with the frequency fDTMF = fxtal is output on the derivative port line DP1.7/DCO. The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 13, Table 24. 6.4 Frequency registers Table 6
PCA3354C; PCD3354A
DTMF standard frequencies and their implementation; value = LGF, HGF contents FREQUENCY (Hz) STANDARD 697 770 852 941 1209 1336 1477 1633 GENERATED 697.90 770.46 850.45 943.23 1206.45 1341.66 1482.21 1638.24 DEVIATION (%) 0.13 0.06 -0.18 0.24 -0.21 0.42 0.35 0.32 (Hz) 0.90 0.46 -1.55 2.23 -2.55 5.66 5.21 5.24
VALUE (HEX) DD C8 B5 A3 7F 72 67 5D Table 7
The two frequency registers HGF and LGF define two frequencies. From these, the digital sine synthesizers together with the Digital-to-Analog Converters (DACs) construct two sine waves. Their amplitudes are precisely scaled according to the bandgap voltage reference. This ensures tone output levels independent of supply voltage and temperature. The amplitude of the Low Group Frequency sine wave is attenuated by 2 dB compared to the amplitude of the High Group Frequency sine wave. The two sine waves are summed and then filtered by an on-chip switched capacitor and RC low-pass filters. These guarantee that all DTMF tones generated fulfil the CEPT recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. The value 00H in a frequency register stops the corresponding digital sine synthesizer. If both frequency registers contain 00H, the whole frequency generator is shut off, resulting in lower power consumption. The frequency `f' of the sine wave generated from either of the frequency registers is a function of the clock frequency `fxtal' and the decimal value `x' held in the register. The equation relating these variables is: f xtal f = --------------------------------; where 60 x 255. [ 23 ( x + 2 ) ] The frequency limitation given by x 60 is due to the low-pass filters which would attenuate higher frequency sine waves. 6.5 DTMF frequencies
Dialling symbols, corresponding DTMF frequency pairs and frequency register contents LGF VALUE (HEX) A3 DD DD DD C8 C8 C8 B5 B5 B5 DD C8 B5 A3 A3 A3 HGF VALUE (HEX) 72 7F 72 67 7F 72 67 7F 72 67 5D 5D 5D 5D 7F 67
TELEPHONE DTMF FREQ. KEYBOARD PAIRS SYMBOLS (Hz) 0 1 2 3 4 5 6 7 8 9 A B C D * # (941, 1336) (697, 1209) (697, 1336) (697, 1477) (770, 1209) (770, 1336) (770, 1477) (852, 1209) (852, 1336) (852, 1477) (697, 1633) (770, 1633) (852, 1633) (941, 1633) (941, 1209) (941, 1477)
Assuming an oscillator frequency fxtal = 3.58 MHz, the DTMF standard frequencies can be implemented as shown in Table 6. The relationship between telephone keyboard symbols, DTMF frequency pairs and the corresponding frequency register contents are given in Table 7.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
6.6 Modem frequencies Table 9
PCA3354C; PCD3354A
Musical scale frequencies and their implementation HGF VALUE (HEX) F8 EA DD D0 C5 B9 AF A5 9C 93 8A 82 7B 74 6D 67 61 5C 56 51 4D 48 44 40 3D FREQUENCY (Hz) STANDARD(1) 622.3 659.3 698.5 740.0 784.0 830.6 880.0 923.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.7 1975.5 2093.0 2217.5 2349.3 2489.0 GENERATED 622.5 659.5 697.9 741.1 782.1 832.3 879.3 931.9 985.0 1044.5 1111.7 1179.0 1245.1 1318.9 1402.1 1482.2 1572.0 1655.7 1768.5 1875.1 1970.0 2103.3 2223.3 2358.1 2470.4
Again assuming an oscillator frequency fxtal = 3.58 MHz, the standard modem frequencies can be implemented as in Table 8. It is suggested to define the frequency by the HGF register while the LGF register contains 00H, disabling Low Group Frequency generation. Table 8 HGF VALUE (HEX) 9D 82 8F 79 80 45 76 48 5C 52 4B 44 Notes 1. Standard is V.21. 2. Standard is Bell 103. 3. Standard is Bell 202. 4. Standard is V.23. 6.7 Musical scale frequencies Standard modem frequencies and their implementation FREQUENCY (Hz) MODEM 980(1) 1180(1) 1070(2) 1270(2) 1200(3) 2200(3) 1300(4) 2100(4) 1650(1) 1850(1) 2025(2) 2225(2) GENERATED 978.82 1179.03 1073.33 1265.30 1197.17 2192.01 1296.94 2103.14 1655.66 1852.77 2021.20 2223.32 DEVIATION (%) -0.12 -0.08 0.31 -0.37 -0.24 -0.36 -0.24 0.15 0.34 0.15 -0.19 -0.08 (Hz) -1.18 -0.97 3.33 -4.70 -2.83 -7.99 -3.06 3.14 5.66 2.77 -3.80 -1.68
NOTE D#5 E5 F5 F#5 G5 G#5 A5 A#5 B5 C6 C#6 D6 D#6 E6 F6 F#6 G6 G#6 A6 A#6 B6 C7 C#7 D7 D#7 Note
Finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency fxtal = 3.58 MHz (Table 9). It is suggested to define the frequency by the HGF register while the LGF contains 00H, disabling Low Group Frequency generation.
1. Standard scale based on A4 @ 440 Hz.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
7 EEPROM AND TIMER 2 ORGANIZATION
PCA3354C; PCD3354A
Whereas read access times to an EEPROM are comparable to RAM access times, write and erase accesses are much slower at 5 ms each. To make these operations more efficient, several provisions are available in the PCA3354C; PCD3354A. First, the EEPROM array is structured into 64 four-byte pages (see Fig.4) permitting access to 4 bytes in parallel (write page, erase/write page and erase page). It is also possible to erase and write individual bytes. Finally, the EEPROM address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. To simplify the erase and write timing, the derivative 8-bit down-counter (Timer 2) with reload register is provided. In addition to EEPROM timing, Timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths.
The PCA3354C; PCD3354A have 256 bytes of Electrically Erasable Programmable Read Only Memory (EEPROM). Such non-volatile storage provides data retention without the need for battery backup. In telecom applications, the EEPROM is used for storing redial numbers and for short dialling of frequently used numbers. More generally, EEPROM may be used for customizing microcontrollers, such as to include a PIN code or a country code, to define trimming parameters, to select application features from the range stored in ROM. The most significant difference between a RAM and an EEPROM is that a bit in EEPROM, once written to a logic 1, cannot be cleared by a subsequent write operation. Successive write accesses actually perform a logical OR with the previously stored information. Therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. Thus, an erase-and-write operation is the EEPROM equivalent of a RAM write operation.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
handbook, full pagewidth
6 8 EEPROM ADDRESS REGISTER
2 2 : 4 DECODER EEPROM LATCH 0 EEPROM LATCH 1 EEPROM LATCH 2 EEPROM LATCH 3 F0 F1 F2 F3 256-byte EEPROM ARRAY (64 4-byte PAGES) 6 : 64 DECODER
8
8 8 EEPROM TEST REGISTER
8 EEPROM CONTROL REGISTER
8 TIMER 2 RELOAD REGISTER 8 8 TIMER 2 REGISTER (T2) 8 INTERNAL BUS
1 f 480 xtal
MGB783
T2F set on underflow
Fig.4 Block diagram of the EEPROM and Timer 2.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
7.1 7.1.1 EEPROM registers EEPROM CONTROL REGISTER (EPCR)
PCA3354C; PCD3354A
The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register. See Tables 10, 11 and 12. Table 10 EEPROM Control Register (address 04H, access type R/W) 7 STT2 6 ET2I 5 T2F 4 EWP 3 MC3 2 MC2 1 MC1 0 0
Table 11 Description of the EPCR bits BIT 7 6 5 4 3 2 1 0 SYMBOL STT2 ET2I T2F EWP MC3 MC2 MC1 - This bit is set to a logic 0. DESCRIPTION Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2 decrements from reload value. Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1, then T2F event can request interrupt. Timer 2 flag. Set when T2 underflows (or by program); reset by program. Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or write and Timer 2). Reset at the end of EEPROM erase and/or write. Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as shown in Table 12.
Table 12 Mode selection; X = don't care EWP 0 0 1 1 1 X X X MC3 0 0 0 1 1 0 1 1 MC2 0 1 1 0 1 0 0 1 MC1 0 0 X 0 1 1 1 0 read byte increment mode write page erase/write page erase page not allowed DESCRIPTION
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
7.1.2 EEPROM ADDRESS REGISTER (ADDR)
PCA3354C; PCD3354A
The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed. As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero. Table 13 EEPROM Address Register (address 01H, access type R/W) 7 0 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
Table 14 Description of ADDR bits BIT 7 6 to 2 1 to 0 SYMBOL - AD6 to AD2 AD1 to AD0 This bit is set to a logic 0. AD2 to AD6 select one of 32 pages. AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0 and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1 increments after every write to an EEPROM latch, thus enhancing access to sequential EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when AD0 and AD1 are both a logic 1. DESCRIPTION
7.1.3
EEPROM DATA REGISTER (DATR)
Table 15 EEPROM Data Register (address 03H; access type R/W) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 16 Description of DATR bits BIT 7 to 0 SYMBOL D7 to D0 DESCRIPTION The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write operation to DATR, loads data into the EEPROM latch (see Fig.4) defined by bits AD0 and AD1 of ADDR.
7.1.4
EEPROM TEST REGISTER (TST)
The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the device user.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
7.2 EEPROM latches
PCA3354C; PCD3354A
page, are irrelevant during write and erase cycles. However, write and erase cycles need not affect all bytes of the page. The EEPROM flags F0 to F3 (see Fig.4) determine which bytes within the EEPROM page are affected by the erase and/or write cycles. A byte whose corresponding EEPROM flag is zero remains unchanged. With erase page, a byte is erased if its corresponding EEPROM flag is set. With write page, data in EEPROM latches 0 to 3 (Fig.4) are ORed to the individual page bytes if and only if the corresponding EEPROM flags are set. In an erase/write cycle, F0 to F3 select which page bytes are erased and ORed with the corresponding EEPROM latches. ORing, in this event, means that the EEPROM latches are copied to the selected page bytes. The described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. This advantage necessitates a preparation step, called page setup, before the actual erase and/or write cycle can be executed. Page setup controls EEPROM latches and EEPROM flags. This will be described in the Sections 7.5.1 to 7.5.5. 7.5.1 PAGE SETUP
The four EEPROM latches (EEPROM Latch 0 to 3; Fig.4) cannot be read by user software. Due to their construction, the latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of any EEPROM cycle. 7.3 EEPROM flags
The four EEPROM flags (F0 to F3; Fig.4) cannot be directly accessed by user software. An EEPROM flag is set as a side-effect when the corresponding EEPROM latch is written through DATR. The EEPROM flags are reset at the conclusion of any EEPROM cycle. 7.4 EEPROM macros
The instruction sequence used in an EEPROM access should be treated as an indivisible entity. Erroneous programs result if ADDR, DATR, RELR or EPCR are inadvertently changed during an EEPROM cycle or its setup. Special care should be taken if the program may asynchronously divert due to an interrupt. A new access to the EEPROM may only be initiated when no write, erase or erase/write cycles are in progress. This can be verified by reading bit EWP (register EPCR). For write, erase and erase/write cycles, it is assumed that the Timer 2 Reload Register (RELR) has been loaded with the appropriate value for a 5 ms delay, which depends on fxtal (see Table 23). The end of a write, erase or erase/write cycle will be signalled by a cleared EWP and by a Timer 2 interrupt provided that ET2I = 1 and that the derivative interrupt is enabled. 7.5 EEPROM access
Page setup is a preparation step required before write page, erase page and erase/write page cycles. As previously described, these page operations include single-byte write, erase and erase/write as a special event. EEPROM flags F0 to F3 determine which page bytes will be affected by the mentioned page operations. EEPROM Latch 0 to 3 must be preset through DATR to specify the write cycle data to EEPROM and to set the EEPROM flags as a side-effect. Obviously, the actual preset value of the EEPROM latches is irrelevant for erase page. Preset of one, two, three or all four EEPROM latches and the corresponding EEPROM flags can be performed by repeatedly defining ADDR and writing to DATR (see Table 17). If more than one EEPROM latch must be preset, the subcounter consisting of AD0 and AD1 can be induced to auto-increment after every write to DATR, thus stepping through all EEPROM latches. For this purpose, increment mode (Table 12) must be selected. Auto-incrementing stops at EEPROM Latch 3. It is not mandatory to start at EEPROM Latch 0 as in shown in Table 18. Note that AD2 to AD6 are irrelevant during page setup. They will usually specify the intended EEPROM page, anticipating the subsequent page cycle. 15
One read, one write, one erase/write and one erase access are defined by bits EWP and MC1 to MC3 in the EPCR register; see Table 10. Read byte retrieves the EEPROM byte addressed by ADDR when DATR is read. Read cycles are instantaneous. Write and erase cycles take 5 ms, however. Erase/write is a combination of an erase and a subsequent write cycle, consequently taking 10 ms. As their names imply, write page, erase page and erase/write page are applied to a whole EEPROM page. Therefore, bits AD0 and AD1 of register ADDR (see Table 13), defining the byte location within an EEPROM
1996 Dec 18
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
From now on, it will be assumed that AD2 to AD6 will contain the intended EEPROM page address after page setup. Table 17 Page setup; preset INSTRUCTION MOV A, #addr MOV ADDR, A MOV A, #data MOV DATR, A RESULT address of EEPROM latch send address to ADDR load write, erase/write or erase data send data to addressed EEPROM latch
PCA3354C; PCD3354A
latches, the corresponding bytes in the page should previously have been erased. The EEPROM latches are preset as described in Section 7.5.1. The actual transfer to the EEPROM is then performed as shown in Table 20. The last instruction also starts Timer 2. The data in the EEPROM latches are ORed with that in the corresponding page bytes within 5 ms. A single-byte write is simply a special case of `write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by bits AD2 to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1). This allows efficient coding of multi-page write operations. Table 20 Write page INSTRUCTION MOV A, #EWP + MC2 MOV EPCR, A 7.5.4 RESULT `write page' control word start `write page' cycle
Table 18 Page setup; auto-incrementing INSTRUCTION MOV A, #MC2 MOV EPCR, A MOV A, #baddr MOV ADDR, A MOV A, R0 MOV DATR, A MOV A, R1 MOV DATR, A MOV A, R2 MOV DATR, A MOV A, R3 MOV DATR, A 7.5.2 READ BYTE RESULT increment mode control word select increment mode EEPROM Latch 0 address (AD0 = AD1 = 0) send EEPROM Latch 0 address to ADDR load 1st byte from Register 0 send 1st byte to EEPROM Latch 0 load 2nd byte from Register 1 send 2nd byte to EEPROM Latch 1 load 3rd byte from Register 2 send 3rd byte to EEPROM Latch 2 load 4th byte from Register 3 send 4th byte to EEPROM Latch 3
ERASE/WRITE PAGE
The EEPROM latches are preset as described in Section 7.5.1. The page byte corresponding to the asserted flags (among F0 to F3) are erased and re-written with the contents of the respective EEPROM latches. The last instruction also starts Timer 2. Erasure takes 5 ms upon which Timer Register T2 reloads for another 5 ms cycle for writing. The top cycles together take 10 ms. A single-byte erase/write is simply a special event of `erase/write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by AD2 to AD6) and to EEPROM Latch 0 (by AD0 and AD1). This allows efficient coding of multi-page erase/write operations. Table 21 Erase/write page INSTRUCTION MOV A, #EWP + MC3 MOV EPCR, A RESULT `erase/write page' control word start `erase/write page' cycle
Since ADDR auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. Table 19 Read byte INSTRUCTION MOV A, #RDADDR MOV ADDR, A MOV A, DATR 7.5.3 WRITE PAGE RESULT load read address send address to ADDR read EEPROM data
The write cycle performs a logical OR between the data in the EEPROM latches and that in the addressed EEPROM page. To actually copy the data from the EEPROM 1996 Dec 18 16
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
7.5.5 ERASE PAGE
PCA3354C; PCD3354A
The second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding EEPROM cycle. Timer 2 is stopped, T2F is set whereas EWP and MC1 to MC3 are cleared. Table 23 Reload values as a function of fxtal fxtal (MHz) 1 2 3.58 6 10.74 16 Note 1. The reload value is (5 x 10-3 x 1480 x fxtal) - 1; fxtal in MHz. 7.6.2 TIMER 2 AS A GENERAL PURPOSE TIMER RELOAD VALUE(1) (HEX) 0A 14 25 3E 6F A6
The EEPROM flags are set as described in Section 7.5.1. The corresponding page bytes are erased. The last instruction also starts Timer 2. Erasure takes 5 ms. A single-byte erase is simply a special case of `erase page'. Note that ADDR does not auto-increment after an erase cycle. Table 22 Erase page INSTRUCTION RESULT
MOV A, #EWP + MC3 + MC2 + MC1 `erase page' control word MOV EPCR, A start `erase page' cycle
7.6
Timer 2
Timer 2 is a 8-bit down-counter decremented at a rate of 1 480 x fxtal. It may be used either for EEPROM timing or as a general purpose timer. Conflicts between the two applications should be carefully avoided. 7.6.1 TIMER 2 FOR EEPROM TIMING
When used for EEPROM timing, Timer 2 serves to generate the 5 ms intervals needed for erasing or writing the EEPROM. At the decrement rate of 1480 x fxtal, the reload value for a 5 ms interval is a function of fxtal. Table 23 summarizes the required reload values for a number of oscillator frequencies. Timer 2 is started by setting bit EWP in the EPCR. The Timer Register T2 is loaded with the reload value from RELR. T2 decrements to zero. For an erase/write cycle, underflow of T2 indicates the end of the erase operation. Therefore, Timer Register T2 is reloaded from RELR for another 5 ms interval during which the flagged EEPROM latches are copied to the corresponding bytes in the page addressed by ADDR.
When used for purposes other than EEPROM timing, Timer 2 is started by setting STT2. The Timer 2 Register T2 (see Table 25) is loaded with the reload value from RELR. T2 decrements to zero. On underflow, T2 is reloaded from RELR, T2F is set and T2 continues to decrement. Timer 2 can be stopped at any time by clearing STT2. The value of T2 is then held and can be read out. After setting STT2 again, Timer 2 decrements from the reload value. Alternatively, it is possible to read T2 `on the fly' i.e. while Timer 2 is operating.
1996 Dec 18
17
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
8 DERIVATIVE INTERRUPTS 11 IDLE MODE
PCA3354C; PCD3354A
One derivative interrupt event is defined. It is controlled by bits T2F and ET2I in the EPCR (see Tables 10 and 11). The derivative interrupt event occurs when T2F is set. This request is honoured under the following circumstances: * No interrupt routine proceeds * No external interrupt request is pending * The derivative interrupt is enabled * ET2I is set. The derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing T2F. If the derivative interrupt is not used, T2F may directly be tested by the program. Obviously, T2F can also be asserted under program control, e.g. to generate a software interrupt. 9 TIMING
In Idle mode, the frequency generator, the EEPROM and the Timer 2 sections remain operative. Therefore, the IDLE instruction may be executed while an erase and/or write access to EEPROM is in progress. 12 STOP MODE Since the oscillator is switched off, the frequency generator, the EEPROM and the Timer 2 sections receive no clock. It is suggested to clear both the HGF and the LGF registers before entering stop mode. This will cut off the biasing of the internal amplifiers, considerably reducing current requirements. The Stop mode must not be entered while an erase and/or write access to EEPROM is in progress. The STOP instruction may only be executed when EWP in EPCR is zero. The Timer 2 section is frozen during Stop mode. After exit from Stop mode by a HIGH level on CE/T0, Timer 2 proceeds from the held state.
Although the PCA3354C; PCD3354A operate over a clock frequency range from 1 MHz to 16 MHz, fxtal = 3.58 MHz or 10.74 MHz will usually be chosen to take full advantage of the frequency generator section. 10 RESET In addition to the conditions given in the "PCD33xxA Family" data sheet, all derivative registers are cleared in the reset state.
1996 Dec 18
18
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
13 SUMMARY OF I/O PORTS AND MASK OPTIONS
PCA3354C; PCD3354A
All standard quasi-bidirectional I/O ports are available; see "PCD33xxA Family" data sheet. * Port 0: 8 parallel port lines P0.0 to P0.7 * Port 1: 8 parallel port lines P1.0 to P1.7 * Port 2: 4 parallel port lines P2.0 to P2.3. In addition to the standard ports, 2 derivative I/O ports are available: * Derivative Port 0: 8 parallel port lines DP0.0 to DP0.7 (register DP0L) * Derivative Port 1: 8 parallel port lines DP1.0 to DP1.7 (register DP1L). The port options and the other ROM mask options are listed in Table 24. See Table 25 for the addresses of DP0L and DP1L. Table 24 ROM mask options FUNCTION IMPLEMENTED IN ROM Program/data Port Output P0.0 to P0.7 P1.0 to P1.6 P1.7/MDY; note 1 P2.0 to P2.3 DP0.0 to DP0.7 DP1.0 to DP1.6 DP1.7/DCO; note 2 Port State after reset P0.0 to P0.7 P1.0 to P1.6 P1.7/MDY P2.0 to P2.3 DP0.0 to DP0.7 DP1.0 to DP1.6 DP1.7/DCO Oscillator Transconductance Power-on-reset Power-on-reset voltage level: VPOR Notes 1. If standard (Option 1) or push-pull (Option 3) output is chosen, the P1.7/MDY output becomes a push-pull output. If open-drain (Option 2) is chosen the P1.7/MDY output becomes an open-drain output. 2. If standard (Option 1) or push-pull (Option 3) output is chosen, the DP1.7/DCO output becomes a push-pull output. If open-drain (Option 2) is chosen the DP1.7/DCO output becomes an open-drain output. 1.2 to 3.6 V in increments of 100 mV; OFF LOW (gmL) MEDIUM (gmM) HIGH (gmH) set set set set set set set reset reset reset reset reset reset reset - - - - - - - standard standard standard standard standard standard standard open-drain open-drain open-drain open-drain open-drain open-drain open-drain push-pull push-pull push-pull push-pull push-pull push-pull push-pull OPTION Any mix of instructions and data up to ROM size of 8 kbytes.
1996 Dec 18
19
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
14 SUMMARY OF DERIVATIVE REGISTERS Table 25 Register map ADDR. (HEX) 00 01 02 03 04 05 06 07 not used EEPROM Address Register (ADDR) not used EEPROM Data Register (DATR) EEPROM Control Register (EPCR) Timer 2 Reload Register (RELR) Timer 2 Register (T2) Test Register (TST) High Group Frequency Register (HGF) Low Group Frequency Register (LGF) Clock and Melody Control Register (MDYCON) Derivative Port 0 lines (DP0L) Derivative Port 1 lines (DP1L) Derivative Port 0 flip-flop (DP0FF) Derivative Port 1 flip-flop (DP1FF) D7 STT2 R7 T2.7 D6 ET21 R6 T2.6 D5 TF2 R5 T2.5 D4 EWP R4 T2.4 0 AD6 AD5 AD4 REGISTER 7 6 5 4
PCA3354C; PCD3354A
3
2
1
0
R/W
AD3
AD2
AD1
AD0
R/W
D3 MC3 R3 T2.3
D2 MC2 R2 T2.2
D1 MC1 R1 T2.1
D0 0 R0 T2.0
R/W R/W R/W R
only for test purposes; not to be accessed by the device user
08 to 10 not used 11 12 13 H7 L7 0 H6 L6 0 H5 L5 0 H4 L4 0 H3 L3 0 H2 L2 DCO H1 L1 DIV3 H0 L0 EMO W W R/W
14 to 2F not used 30 31 32 33 D0.7 D1.7 F0.7 F1.7 D0.6 D1.6 F0.6 F1.6 D0.5 D1.5 F0.5 F1.5 D0.4 D1.4 F0.4 F1.4 D0.3 D1.3 F0.3 F1.3 D0.2 D1.2 F0.2 F1.2 D0.1 D1.1 F0.1 F1.1 D0.0 D1.0 F0.0 F1.0 R R R/W R/W
34 to FF not used
1996 Dec 18
20
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
15 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot PO ISS Tstg Tj 16 HANDLING supply voltage all input voltages DC input current DC output current total power dissipation power dissipation per output ground supply current storage temperature operating junction temperature PARAMETER
PCA3354C; PCD3354A
MIN. -0.8 -0.5 -10 -10 - - -50 -65 -
MAX. +7.0 +10 +10 125 30 +50 +150 90 V VDD + 0.5 V
UNIT
mA mA mW mW mA C C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see "Data Handbook IC14, Section: Handling MOS devices").
1996 Dec 18
21
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
17 DC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = 0 to +50 C (PCA3354C) or -25 to +70 C (PCD3354A); all voltages with respect to VSS; fxtal = 3.58 MHz (gmL); unless otherwise specified. SYMBOL Supply VDD supply voltage operating RAM data retention in Stop mode IDD operating supply current see Figs 6 and 7; note 2 VDD = 3 V; value HGF or LGF 0 VDD = 3 V; value HGF = LGF = 0 VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF or LGF 0; DIV3 = 1 VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF = LGF = 0 VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 IDD(idle) supply current (Idle mode) see Figs 8 and 9; note 2 VDD = 3 V; value HGF or LGF 0 VDD = 3 V; value HGF = LGF =0 VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF or LGF 0; DIV3 = 1 VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF = LGF = 0 VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 IDD(stp) supply current (Stop mode) See Fig.10; notes 2 and 3 VDD = 1.8 V; Tamb = 25 C VDD = 1.8 V; Tamb = -25 to +70 C Inputs VIL VIH ILI IOL IOH IOH1 LOW level input voltage HIGH level input voltage input leakage current VSS VI VDD VDD = 3 V; VO = 0.4 V; see Fig.11 VDD = 3 V; VO = 2.7 V; see Fig.12 VDD = 3 V; VO = 0 V; see Fig.12 VDD = 3 V; VO = 2.6 V; see Fig.13 0 -1 - - 0.3VDD V VDD +1 - - -300 - V A 0.7VDD - - - 1.0 - 5.5 10 A A - - - - - 0.7 0.25 2.3 1.3 2.4 1.4 0.5 5.5 3.5 - mA mA mA mA mA - - - - - 0.8 0.35 2.7 1.7 3.5 1.6 0.7 6.2 4.2 - mA mA mA mA mA see Fig.5 note 1 1.8 1.0 - - 6 6 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Port outputs LOW level output sink current HIGH level pull-up output source current HIGH level push-pull output source current 0.7 -10 - -0.7 3.5 -30 -140 -3.5 mA A A mA
1996 Dec 18
22
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
SYMBOL PARAMETER CONDITIONS
PCA3354C; PCD3354A
MIN.
TYP.
MAX.
UNIT
TONE output (see Fig.14; notes 1 and 4) VHG(RMS) VLG(RMS) f f VDC ZO Gv THD HGF voltage (RMS values) LGF voltage (RMS values) frequency deviation DC voltage level output impedance pre-emphasis of group total harmonic distortion Tamb = 25 C; note 5 note 7 158 125 -0.6 - - 1.5 - 105 10 -0.5 1.7 181 142 - 0.5VDD 100 2.0 -25 - - 205 160 0.6 - 500 2.5 - - - years mV mV % V dB dB
EEPROM (notes 1 and 6) ncyc tret VPOR VPOR gmL gmM gmH RF endurance (erase/write cycles) data retention
Power-on-reset (see Fig.15) Power-on-reset level variation around chosen VPOR Power-on-reset level note 8; for PCD3354A note 9; for PCA3354C 0 2.0 +0.5 2.3 V V
Oscillator (see Fig.16) LOW transconductance MEDIUM transconductance HIGH transconductance feedback resistor VDD = 5 V VDD = 5 V VDD = 5 V 0.2 0.9 3 0.3 0.4 1.6 4.5 1.0 1.0 3.2 9.0 3.0 mS mS mS M
Notes to the DC characteristics 1. TONE output; EEPROM erase and write require VDD 2.5 V: a) TONE output requires fxtal < 4 MHz in case DIV3 = 0. b) TONE output requires fxtal < 12 MHz in case DIV3 = 1. 2. VIL = VSS; VIH = VDD; open-drain outputs connected to VSS; all other outputs open: a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit. b) Typical values: Tamb = 25 C; crystal connected between XTAL1 and XTAL2. 3. VIL = VSS; VIH = VDD; RESET, T1 and CE/T0 at VSS; crystal connected between XTAL1 and XTAL2; open-drain outputs connected to VSS; all other outputs open.
4. Values are specified for DTMF frequencies only (CEPT). 5. Related to the Low Group Frequency (LGF) component (CEPT). 6. After final testing the value of each EEPROM bit is typically logic 1. 7. Verified on sampling basis. 8. VPOR is an option chosen by the user. Depending on its value, it may restrict the supply voltage range. 9. Each device is tested on the condition: VDD(min) < VPOR; to ensure a correct start-up, even for slow rising supply voltages.
1996 Dec 18
23
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
handbook, halfpage f
18 xtal (MHz) 15
MLA493
MGB813
handbook, halfpage
6
IDD (mA) 10.7 MHz HGF LGF = 0 gmM 16 MHz HGF = LGF = 0 gmH -25 oC to 70 oC 2 3.58 MHz HGF LGF gmL 10.7 MHz HGF = LGF = 0 gmM 3.58 MHz HGF = LGF = 0 gmL 1 3 5 VDD (V) 7 0 1 3 5 VDD (V) 7
12
4
9 guaranteed operating range
6
3
0
Measured with crystal between XTAL1 and XTAL2.
Fig.5
Maximum clock frequency (fxtal) as a function of supply voltage (VDD).
Fig.6
Typical operating supply current (IDD) as a function of supply voltage (VDD).
handbook, halfpage
6
MGB828
MGB814
handbook, halfpage
6
IDD (mA) 4 5V
IDD(idle) (mA) 16 MHz HGF = LGF = 0 gmH -25 oC to 70 oC
4
2
2
10.7 MHz HGF LGF = 0 gmM
3V 0 1 10 fxtal (MHz) 10
2
0 1 3 5
3.58 MHz HGF LGF gmL 10.7 MHz HGF = LGF = 0 gmM 3.58 MHz HGF = LGF = 0 gmL VDD (V) 7
Measured with function generator on XTAL1.
Measured with crystal between XTAL1 and XTAL2.
Fig.7
Typical operating supply current (IDD) as a function of clock frequency (fxtal).
Fig.8
Typical supply current in Idle mode (IDD(idle)) as a function of supply voltage (VDD).
1996 Dec 18
24
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
handbook, halfpage
6
MGB830
MGB826
handbook, halfpage
6
IDD(idle) (mA) 4
IDD(stp) (A) 5
4
3
2
5V
2
1
3V 0 1 10 fxtal (MHz) 10
2
0 1 3 5 VDD (V) 7
Measured with function generator on XTAL1.
Fig.9
Typical supply current in Idle mode (IDD(idle)) as a function of clock frequency (fxtal).
Fig.10 Typical supply current in Stop mode (IDD(stp)) as a function of supply voltage (VDD).
MGB831
handbook, halfpage
12
handbook, halfpage
-300
MGB832
IOL (mA) 8
IOH (A) -200
VO = 0 V
4
-100 VO = 0.9VDD
0 1 3 5 VDD (V) 7
0 1 3 5 VDD (V) 7
VO = 0.4 V.
Fig.11 Typical LOW level output sink current (IOL) as a function of supply voltage (VDD).
Fig.12 Typical HIGH level pull-up output source current (IOH) as a function of supply voltage (VDD).
1996 Dec 18
25
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
handbook, halfpage
-12
MGB833
IOH1 (mA) -8
handbook, halfpage VDD
DEVICE TYPE NUMBER (1)
-4
TONE
1 F
50 pF
10 k
VSS
MGB835
0 1
VO = VDD - 0.4 V.
3
5
VDD (V)
7
Fig.13 Typical HIGH level push-pull output source current (IOH1) as a function of supply voltage (VDD).
(1)
Device type number: PCA3354C or PCD3354A.
Fig.14 TONE output test circuit.
MGD495
handbook, halfpage
6
handbook, halfpage
10
MGB818
VDD (V)
gmH gm (mS) gmM 1
4
VPOR = 2.0 V 2 VPOR = 1.3 V
gmL
0 -25
10
1
25
75 125 Tamb (C) 70
1
3
5
VDD (V)
7
Fig.15 Typical Power-on-reset level (VPOR) as function of ambient temperature (Tamb).
Fig.16 Typical transconductance (gm) as a function of supply voltage (VDD).
1996 Dec 18
26
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
PCA3354C; PCD3354A
18 AC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = 0 to +50 C (PCA3354C) or -25 to +70 C (PCD3354A); all voltages with respect to VSS; unless otherwise specified. SYMBOL tr tf fxtal PARAMETER rise time all outputs fall time all outputs clock frequency see Fig.5 CONDITIONS VDD = 5 V; Tamb = 25 C; CL = 50 pF - - 1 MIN. TYP. 30 30 - MAX. - - 16 UNIT ns ns MHz
1996 Dec 18
27
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
19 PACKAGE OUTLINE
PCA3354C; PCD3354A
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L A A2 A1
Q (A 3) Lp
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 Q 1.2 0.9 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Dec 18
28
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
20 SOLDERING 20.1 Introduction
PCA3354C; PCD3354A
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 20.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 20.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1996 Dec 18
29
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
21 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCA3354C; PCD3354A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 22 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Dec 18
30
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator and 256 bytes EEPROM
NOTES
PCA3354C; PCD3354A
1996 Dec 18
31
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417021/1200/04/pp32
Date of release: 1996 Dec 18
Document order number:
9397 750 01082

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